CAMs are used in a variety of applications. They differ from RAM (Random Access Memory) because a RAM is presented an address and reads or writes data, whereas a CAM is capable of, among other things, being presented data and sensing if a matching entry is stored. In order to determine quickly if there is a matching entry, many locations may have to be checked simultaneously. This may consume large amounts of power and may slow the comparison. This presents a problem.
Additionally since may location may be checked simultaneously, this may lead to cross-coupling interference which may affect the performance of a CAM. This presents a problem.
FIG. 1 illustrates one CAM cell (CC) with a word line (WLm), a match line (MLm), data inputs for reading and writing (Dn and Dn*), and compare data lines (CDn and CDn*).
FIG. 2 shows an array of CAM cells of dimension n columns by m rows. Each row of cells has a common word line, a common match line, and a single sense amplifier at the end of a row of CAM cells. For example, row 0 has word line WL0 which communicates to CAM cells (CC) connected to data line pairs, DO/DO*, D1/D1*, D2/D2*, through Dn/Dn*. The match line ML0 is also in communication with the CAM cells connected to these data line pairs and ML0 communicates with sense amplifier 0 SA0 located substantially at the end of the row of CAM cells (CC). This arrangement is repeated for m word lines WLm, for m match lines MLm, and for m sense amplifiers Sam (i.e. WL0, WL1, WL2, . . . , WLm, the corresponding ML0, ML1, ML2, . . . , MLm, and the corresponding SA0, SA1, SA2, . . . , SAm). Since there is one match line per row and one sense amplifier per row at the end of a row of a CAM array, many CAM cells are connected to a single match line. Capacitance on this line may be large and as a result the sense amplifier may be slow in responding to signal changes. This may present a problem.
FIG. 3 shows an approach 300 trying to overcome some of the problems associated with the approach shown in FIG. 2. Here in FIG. 3, the CAM array is divided into sub-arrays (for example, Sub-Array A and Sub-Array B). In each row and in between two sub-arrays, is one sense amplifier (such as SA0) which receives two match lines one from the left (such as Sub-Array A, ML0A) and the other from right (such as Sub-Array B, ML0B). Because a particular match line in FIG. 3 connects to half as many CAM cells as in FIG. 2 for a given array size, the capacitance on each match line (such as ML0A, and ML0B) is approximately half. This results in better speed. However the two input sense amplifier may be larger in die size and may draw higher power than a single input sense amplifier. This may present a problem.
FIG. 4 illustrates a layout 400 for a TCAM cell. For illustrative purposes only straight metal lines are shown, and not interconnects (such as vias). The dashed line indicates a single TCAM cell. This single TCAM cell may be repeated to produce a group of cells. Additionally for illustrative purposes, example metal layers are denoted. Here on metal layer 2 is Low_Match. Running substantially parallel to Low_Match, from left to right, on metal layer 3 is Value_Bit_Line, Value_Bit_Line*, Data_Line*, Data_Line, Mask_Bit_Line, and Mask_Bit_Line*. Running substantially perpendicular to Low_Match, from top to bottom, is Bypass on metal 5, and High_Match line on metal 4. As will be noted Low_Match on metal 2 runs parallel and physically close to Data_Line on metal 3 and Data_Line* on metal 3. This proximity leads to capacitive and inductive coupling between these lines. Additionally the overlap between the Bypass line on metal 5 and Data_Line* on metal 3 and Data_Line on metal 3 leads to coupling between these lines. Also the overlap between the High_Match line on metal 4 and Data_Line* on metal 3 and Data_Line on metal 3 leads to coupling between these lines. This may present a problem.
FIG. 5 illustrates a layout 500 for a TCAM cell. For illustrative purposes only straight metal lines are shown, and only a single via interconnect High_Match Via Pickup is shown. The dashed line indicates a single TCAM cell. This single TCAM cell may be repeated to produce a group of cells. Additionally for illustrative purposes, example metal layers are denoted. Here on metal layer 2 is Low_Match. Running substantially parallel to Low_Match, from left to right, on metal layer 3 is Value_Bit_Line, Value_Bit_Line*, Data_Line*, Data_Line, Mask_Bit_Line, and Mask_Bit_Line*. Running substantially perpendicular to Low_Match, from top to bottom, is Bypass on metal 5, and High_Match line on metal 4. Via interconnect High_Match Via Pickup is shown as a dark dotted box on High_Match and may, for illustrative purposes, be considered to extend normal to the paper surface downward to connect to a device, such as the source of a transistor (for example, see the source of Q22 in FIG. 14). High_Match Via Pickup traverses the metal layers (including metal 3) as it connects to a device in the TCAM cell and is physically close to Data_Line on metal 3 and Data_Line* on metal 3. This proximity leads to capacitive and inductive coupling between these lines. This may present a problem.
FIG. 6 illustrates a layout 600 for a TCAM cell. For illustrative purposes only straight metal lines are shown, and only a single via interconnect Low_Match Via Pickup is shown. The dashed line indicates a single TCAM cell. This single TCAM cell may be repeated to produce a group of cells. Additionally for illustrative purposes, example metal layers are denoted. Here on metal layer 2 is Low_Match. Running substantially parallel to Low_Match, from left to right, on metal layer 3 is Value_Bit_Line, Value_Bit_Line*, Data_Line*, Data_Line, Mask_Bit_Line, and Mask_Bit_Line*. Running substantially perpendicular to Low_Match, from top to bottom, is Bypass on metal 5, and High_Match line on metal 4. Via interconnect Low_Match Via Pickup is shown as a dark dotted box on Low_Match and may, for illustrative purposes, be considered to extend normal to the paper surface downward to connect to a device, such as the drain of a transistor (for example, see the drain of Q26 in FIG. 14). Low_Match Via Pickup traverses the metal layers (including metal 1) as it connects to a device in the TCAM cell and is physically close to Express Mail PO to Addressee: Data_Line on metal 3 and Data_Line* on metal 3. This proximity leads to capacitive and inductive coupling between these lines. This may present a problem.